This invention relates generally to electronic circuits. More particularly, this invention relates to reducing average power in RAM arrays.
As more electronic circuits are included on a single die, the power dissipated by a single die continues to increase. In order to keep the temperature of a single IC (integrated circuit) at a reasonable temperature, many techniques have been used to cool the IC. For example, elaborate cooling fins have been attached to the substrate of ICs. Also, fans have been positioned near a group of IC""s to cool them. In some cases, liquids have been used to reduce the heat produced by ICs. These solutions can be costly and may require a great deal of space, where space is at a premium. If the power on ICs can be reduced while still achieving higher levels of integration, the cost and area of devices that use ICs may be reduced.
The number of bits contained on a semiconductor memory chip, has, on average, quadrupled every three years. As a result, the power that semiconductor memories consume has increased. Computer systems can use large numbers of stand-alone semiconductor memories. Part of the semiconductor memory used by these computer systems, may be held in standby mode for a certain amount of time. The portion of memory that is held in standby is not accessed for data and as result, has lower power requirements than those parts of semiconductor memory that are accessed. The sections of memory that are not being accessed can be monitored. After identifying memory sections that are not being accessed, the power in these sections may be lowered by reducing the voltage applied to them. When sections of memory are being accessed, the voltage may be increased resulting in shorter read and write times. In this manner, power may be directed to sections of memory that may benefit from a higher voltage and power may be directed away from sections that may not need as much power. The following description of an apparatus and method for controlling the voltage applied to individual memory arrays addresses a need in the art to reduce power in ICs and computer systems while maintaining performance requirements.
An embodiment of the invention provides a circuit for controlling power in individual memory arrays of a semiconductor memory. Individual arrays of memory of a semiconductor memory are isolated from a fixed power supply by inserting one or more NFETs and diodes between GND and the negative connection of an individual memory section. The voltage applied to each memory array is controlled by applying a separate variable voltage to each gate of all NFETs connected to a particular memory array. If a memory array is not accessed, the voltage to that section can be lowered, saving power. If a memory array is accessed, the voltage to that section may be raised, providing more power and shortening read and write times. This invention fills a need to reduce overall power on a semiconductor chip while at the same time allowing faster access times.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawing, illustrating by way of example the principles of the invention.